About

Partha Pratim Sarmah is an experienced ASIC Emulation professional currently working at Intel. With 4.43 years of relevant experience, he has a strong background in bringing up RTLs into the Emulation platform using Zebu and Palladium. Partha has a good understanding of the Emulation/fpga flow, including both build and test cases execution flow. He also possesses knowledge of Xilinx Zynq MPSoC and Versal architecture, making him a valuable asset to any team. Partha is well-versed in Verilog, System Verilog, and UVM, and has excellent hands-on experience in system-level debugging using waveform, Verdi, and simvision. He is also proficient in Python and Perl scripting for build flow automation. Partha has worked with various tools such as Zebu Compiler, Palladium, Verdi, Simvision, Vivado, and Cadence incisive. Partha's expertise extends to protocol knowledge, including AXI, AHB, APB, QSPI, UART, and SD. He has a PG Diploma in VLSI Design from c-dac and a Bachelor of Engineering in Electronics and Telecommunication Engineering from Assam Engineering College. In summary, Partha Pratim Sarmah is a dedicated and knowledgeable ASIC Emulation professional with a strong technical background and hands-on experience with various tools and protocols. He is a valuable asset to any team and can contribute significantly to any project.